REDUCING COMPLETION TIME OF LOW VOLTAGE PANELS BY REDUCING BOTTLENECK THROUGH PARALLEL WORKSTATIONS IN PT SCHNEIDER ELECTRIC INDONESIA

Abstract

PT Schneider Electric Indonesia is a leading manufacturer of electrical panels in Indonesia that produces two line of products: Medium Voltage (MV) Panels and Low Voltage (LV) Panels with the latter claimed as their distinctive competency. Despite their success, the company regularly finds lateness in the completion time of their projects in the LV Panels product line. In the recent Project Mogas, PT Schneider Electric Indonesia’s assembly line was 933.57 minutes behind the planning horizon. The lateness resulted a significant cost of IDR 289,081,374.37. The customer’s order was delivered two days late and incurred unnecessary costs. Management needs to analyze the delay, and strive eliminate it. The research focuses on the LV Panels assembly line, particularly for the period of January 2017-June 2017. The research utilizes the comparison of standard and actual cycle time, with the assistance of Process Flowchart and Pareto Analysis to determine the bottleneck. The study shows process “Installing Busbar Non-Standard” paid the highest contribution to total time loss. An improvement proposal is made with “Installing Busbar Non-Standard” as the target; to run two parallel workstations under the problematic process. Predicted results of improvement suggests that PT Schneider Electric Indonesia could save 18,197.98 minutes and IDR 225,067,647.40.